The ultrasmall sensors of the future will monitor our health parameters, vehicles, machines and processes, buildings and smart constructions, and the environment. They will operate autonomously for long periods on a small battery, and they will communicate wirelessly. A key factor for their success, therefore, is their low power consumption, which will define the range of applications and functionalities for which they can be used.
At the 38th European Solid-State Circuits Conference in September, Imec and Holst Centre (Eindhoven, Netherlands) presented four ultralow-power developments to drive next-generation sensors and sensor networks: a frequency-shift-keying receiver for body-area networks, a flexible successive-approximation-register A/D converter for wireless sensor nodes, fast start-up techniques for duty-cycled impulse radio receivers, and a design approach targeting subthreshold operation.
ULP receiver for body-area network applications
Imec and Holst have developed a power-efficient receiver for ULP BAN (ultralow-power body-area network) applications. Whereas most transceivers exploit OOK (on-off keying) modulation, the new receiver uses FSK (frequency-shift keying) modulation and is hence less sensitive to interference. The complete receiver, fabricated in 40-nm CMOS technology, consumes 382.5 μW. The sensitivity measured at a bit error rate of 10−3 is –81 dBm for a 12.5-kbit/sec bit rate. The bit rate is scalable up to 625 kbits/sec, enabling a trade-off between sensitivity and bit rate. Taking advantage of the short-range nature of BAN applications, a mixer-first architecture is proposed, leading to a good dynamic range.
Flexible SAR ADC for ULP wireless sensor nodes
Wireless sensor nodes for electroencephalography, electrocardiography, and temperature and pressure monitoring require ULP ADCs for both the sensor-readout interface and the wireless-communication front end. Each of these applications, however, has its own requirements for accuracy and bandwidth. Imec and Holst Centre have realized a flexible, power-efficient SAR (successive approximation register) ADC that designers can use for a variety of applications. The device supports resolutions from 7 to 10 bits and sample rates from dc to 2M samples/sec; the flexibility is achieved by implementing a reconfigurable comparator and a reconfigurable DAC. The chip, in a 90-nm process, occupies 0.047 mm2, and achieves power efficiencies of 2.8- to 6.6-fJ/conversion step at 2M samples/sec and with a 0.7V supply.
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